View SAA7201H_817790.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

INTEGRATED CIRCUITS
DATA SHEET
SAA7201 Integrated MPEG2 AVG decoder
Objective specification File under Integrated Circuits, IC02 1997 Jan 29
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
FEATURES General * Uses single external Synchronous DRAM (SDRAM) organized as 1M x 16 interfacing at 81 MHz; compatible with the SDRAM `lite' or `PC' * Fast external CPU interface; 16-bit data + 8-bit address * Dedicated input for audio and video data in PES or ES format; data input rate: 9 Mbytes/s in byte mode; 20 Mbit/s in bit serial mode; audio and/or video data can also serve as input via CPU interface * Single 27 MHz external clock for time base reference and internal processing; all required decoding and presentation clocks are generated internally * Internal system time base at 90 kHz can be synchronized via CPU port * Flexible memory allocation under control of the external CPU enables optimized partitioning of memory for different tasks * Boundary scan (JTAG) plus external SDRAM self test implemented * Supply voltage 3.3 V * Package 160 QFP. CPU relation * 16-bit data, 8-bit address, or 16-bit multiplexed bus; Motorola and Intel mode supported * Support for fast DMA transfer to either internal registers or external SDRAM * Maximum sustained rate to the external SDRAM is 9 Mbytes/s. MPEG2 system * Parsing of MPEG2 PES and MPEG1 packet streams * Double System Time Clock (STC) counters for discontinuity handling * Time stamps or CPU controlled audio/video synchronization * Support for seamless time base change (edition) * Processing of errors flagged by channel decoding or demux section * Support for retrieval of PES header and PES private data. MPEG2 audio
SAA7201
* Decoding of 2 channel, layer I and II MPEG audio; support for mono, stereo, intensity stereo and dual channel mode * Constant and variable bit rates up to 448 kbit/s * Audio sampling frequencies: 48, 44.1, 32, 24, 22.05 and 16 kHz * CRC error detection * Selectable output channel in dual channel mode * Independent volume control for both channels and programmable inter-channel crosstalk control through a baseband audio processing unit * Storage ancillary data up to 54 bytes * Dynamic range control at output * Muting possibility via external controller; automatic muting in case of errors * Generation of `beeps' with programmable tone height, duration and amplitude * Serial two channel digital audio output with 16, 18, 20 or 22 bits per sample, compatible with either I2S or Japanese formats * Serial SPDIF audio output * Clock output 256 or 384 x fs for external D/A converter * Audio input buffer in external SDRAM with programmable size (default is 64 kbit) * Programmable processing delay compensation * Software controlled stop, pause, restricted skip, and restart functions. MPEG2 video * Decoding of MPEG2 video up to main level, main profile * Nominal video input buffer size equals 2.6 Mbit for Video Main Profile and Main Level (MP@ML) * Output picture format: CCIR-601 4 : 2 : 2 interlaced pictures; picture format 720 x 576 at 50 Hz or 720 x 480 at 60 Hz * 3 : 2 pull-down supported with 24 and 30 Hz sequences * Support of constant and variable bit rates up to 15 Mbit/s * Output interface at 8-bit wide, 27 MHz UYVY multiplexed bus * Horizontal and vertical pan and scan allows the extraction of a window from the coded picture
1997 Jan 29
2
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
* Flexible horizontal continuous scaling from 0.5 up to 4 allows easy aspect ratio conversion including support for 2.21 : 1 aspect ratio movies * Vertical scaling with fixed factors 0.5, 1 or 2 to support picture scaling and up-sampling * Scaling of incoming pictures to 25% of their original size with anti-aliasing filtering to free screen space for graphics applications like electronic program guides * Non-full screen MPEG pictures will be displayed in a box of which position and background colour are adjustable by the external CPU * Video output may be slaved to internally (master) generated or externally (slave) supplied HV synchronization signals; the position of active video is programmable; MPEG timebase changes do not affected the display phase * Video output direct connectable to SAA718X encoder family * Various trick modes under control of external CPU: - Freeze I or P pictures; restart on I picture - Freeze on B pictures; restart at any moment - Scanning and decoding of I or I and P pictures - Single step mode - Repeat/Skip field for time base correction. Graphics * Graphics is region based and presented in boxes independent of video format * Screen arrangement of boxes is determined by display list mechanism which allows for multiple boxes, background loading, fast switching, scrolling and fading of regions
SAA7201
* Support of 2, 4, 8 bits/pixel bit-maps in fixed bit-maps or coded in accordance to the DVB variable/run length standard for region bases graphics * Optimized memory control in MPEG video decoding allows for storage of graphical bit-maps up to 1.2 Mbit in 50 Hz and 2.0 Mbit in 60 Hz systems * VL/RL encoding enables full screen graphics at 8 bit/pixel in 50 Hz * Fast CPU access enables full bit-map updates within a display field period * Display colours are obtained via colour look-up tables; CLUT output is YUVT at 8-bit for each signal component thus enabling 16M different colours and 6-bit for T (transparency) which gives 64 mixing levels with video * Bit-map table mechanism to specify a sub-set of entries if the CLUT is larger than required by the coded bit pattern; supported bit-map tables are 16 to 256, 4 to 256 and 4 to 16 * Graphics boxes may not overlap vertically; if 256 entry CLUT has to be down loaded, a vertical separation of 1 field line is mandatory * Internal support for fast block moves in the external SDRAM during MPEG decoding * Graphics mechanism can be used for signal generation in the vertical blanking interval; useful for teletext, wide screen signalling, closed caption etc. * Support for a single down-loadable cursor of 1 kpixel with programmable shape; supported shapes are 8 x 128, 16 x 64, 32 x 32, 64 x 16 and 128 x 8 * Cursor colours are determined via a 4-entry CLUT with YUVT at 6, 4, 4 respectively 2 bits; mixing of cursor with video + graphics in 4 levels * Cursor can be moved freely across the screen without overlapping restrictions.
1997 Jan 29
3
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
GENERAL DESCRIPTION The SAA7201 is an MPEG2 decoder which combines audio decoding and video decoding. Additionally to these basic MPEG functions it also provides means for enhanced graphics and/or on-screen display. QUICK REFERENCE DATA SYMBOL VDD VCC IDD(tot) fCLK fCLK PARAMETER functional supply voltage pad supply voltage total supply current at VDD = 3.3 V clock frequency frequency deviation MIN. 3.0 3.0 - - -30 x 10-6 3.3 3.3 tbf 27.0 - TYP.
SAA7201
Due to an optimized architecture for audio and video decoding, maximum capacity in the external memory and processing power from the external CPU is available for the support for graphics.
MAX. 3.6 3.6 - - +30 x 10-6 V V
UNIT
mA MHz
ORDERING INFORMATION TYPE NUMBER SAA7201H PACKAGE NAME QFP160 DESCRIPTION plastic quad flat package; 160 leads (lead length 1.95 mm); body 28 x 28 x 3.4 mm; high stand-off height VERSION SOT322-4
1997 Jan 29
4
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
BLOCK DIAGRAM
SAA7201
handbook, full pagewidth
VDDCO1 to VDDCO4
SDRAM_WE SDRAM_CAS SDRAM_UDQ
SDRAM_DATA (15 to 0)
READI CP81MEXT READO 83 81 80 16
VDDA VDD1 to VDD16 121
SDRAM_RAS 77 4 75 74
SDRAM_ADDR (11 to 0) 78 12 MEMORY INTERFACE
CP81M 16 84
A_STROBE V_STROBE AV_DATA(0 to 7) ERROR
159 148 8 147
AUDIO/VIDEO INTERFACE
VIDEO INPUT BUFFER & SYNC
VIDEO DECODER SYSTEM TIME BASE UNIT CPU_TYPE MUX CS DS AS R/W DTACK ADDRESS(8 to 1) DATA(15 to 0) IRQ(3 to 0) DMA_REQ DMA_ACK DMA_RDY DMA_DONE CLK RESET 4 4 3 6 5 124 138 CLOCK GENERATION AUDIO INPUT BUFFER & SYNC 16 122
MGD322
2 1 8 9 10 11 12 8 16 HOST INTERFACE
SAA7201
106 DISPLAY UNIT 107 HS VS
8 GRAPHICS UNIT YUV(7 to 0) 119 143 142 145 146 139 GRPH SD SCLK WS SPDIF FSCLK
AUDIO DECODER
JTAG 4
VSSCO1 to VSSCO4
VSS1 to VSS16
VSSA
Fig.1 Block diagram.
1997 Jan 29
5
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
PINNING SYMBOL MUX CPU_TYPE DMA_ACK DMA_REQ DMA_DONE DMA_RDY VSS1 CS DS AS R/W DTACK VDD1 IRQ0 IRQ1 IRQ2 IRQ3 VSS2 VSSCO1 VDDCO1 DATA0 DATA1 DATA2 DATA3 VDD2 DATA4 DATA5 DATA6 DATA7 VSS3 DATA8 DATA9 DATA10 DATA11 VDD3 DATA12 DATA13 DATA14 DATA15 VSS4 1997 Jan 29 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 PIN DESCRIPTION multiplexed/non-multiplexed (active LOW) bus input Intel/Motorola (active LOW) selection input DMA acknowledge input DMA request input and output DMA end input DMA ready output ground for pad ring chip select input data strobe input address strobe input read/write (active LOW) input data acknowledge output supply for pad ring individually maskable interrupts individually maskable interrupts individually maskable interrupts individually maskable interrupts ground for pad ring ground for core logic supply for core logic CPU data interface CPU data interface CPU data interface CPU data interface supply for pad ring CPU data interface CPU data interface CPU data interface CPU data interface ground for pad ring CPU data interface CPU data interface CPU data interface CPU data interface supply for pad ring CPU data interface CPU data interface CPU data interface CPU data interface ground for pad ring 6
SAA7201
V 5.0 5.0 3.3 3.3 3.3 3.3 3.3 5.0 5.0 5.0 5.0 5.0 3.3 3.3 3.3 3.3 3.3 - - 3.3 5.0 5.0 5.0 5.0 3.3 5.0 5.0 5.0 5.0 - 5.0 5.0 5.0 5.0 - 5.0 5.0 5.0 5.0 - I I I
I/O
I/O I O/Z - I I I I O/Z - O/Z O/Z O/Z O/Z - - - I/O I/O I/O I/O - I/O I/O I/O I/O - I/O I/O I/O I/O - I/O I/O I/O I/O -
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
SAA7201
SYMBOL ADDRESS1 ADDRESS2 ADDRESS3 ADDRESS4 VDD4 ADDRESS5 ADDRESS6 ADDRESS7 ADDRESS8 VSS5 VSSCO2 VDDCO2 SDRAM_DATA0 SDRAM_DATA15 SDRAM_DATA1 VDD5 SDRAM_DATA14 SDRAM_DATA2 SDRAM_DATA13 VSS6 SDRAM_DATA3 SDRAM_DATA12 SDRAM_DATA4 VDD6 SDRAM_DATA11 SDRAM_DATA5 SDRAM_DATA10 VSS7 SDRAM_DATA6 SDRAM_DATA9 SDRAM_DATA7 VDD7 SDRAM_DATA8 SDRAM_WE SDRAM_CAS VSS8 SDRAM_RAS SDRAM_UDQ VDD8 READI
PIN 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 CPU address interface CPU address interface CPU address interface CPU address interface supply for pad ring CPU address interface CPU address interface CPU address interface CPU address interface ground for pad ring ground for core logic supply for core logic memory data interface memory data interface memory data interface supply for pad ring memory data interface memory data interface memory data interface ground for pad ring memory data interface memory data interface memory data interface supply for pad ring memory data interface memory data interface memory data interface ground for pad ring memory data interface memory data interface memory data interface supply for pad ring memory data interface
DESCRIPTION
V 5.0 5.0 5.0 5.0 3.3 5.0 5.0 5.0 5.0 - - 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 - 3.3 3.3 3.3 3.3 3.3 3.3 3.3 - 3.3 3.3 3.3 3.3 3.3 3.3 3.3 - 3.3 3.3 3.3 3.3 I I I I - I I I I - - -
I/O
I/O I/O I/O - I/O I/O I/O - I/O I/O I/O - I/O I/O I/O - I/O I/O I/O - I/O O O - O O - I
SDRAM write enable output SDRAM column address strobe output ground for pad ring SDRAM row address strobe output SDRAM write mask output supply for pad ring read command input
1997 Jan 29
7
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
SAA7201
SYMBOL READO VSS9 CP81MEXT CP81M VDD9 SDRAM_ADDR8 SDRAM_ADDR9 VSS10 SDRAM_ADDR7 SDRAM_ADDR6 VDD10 SDRAM_ADDR0 SDRAM_ADDR5 SDRAM_ADDR1 VSS11 SDRAM_ADDR4 SDRAM_ADDR2 SDRAM_ADDR3 VSSCO3 VDDCO3 VDD11 TEST8 TEST7 HS VS VSS12 YUV0 YUV1 YUV2 YUV3 VDD12 YUV4 YUV5 YUV6 YUV7 TEST6 GRPH TEST5
PIN 81 82 83 84 85 86 87 89 90 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 read command output ground for pad ring
DESCRIPTION -
V 3.3 3.3 3.3 3.3 3.3 3.3 3.3 - 3.3 3.3 3.3 3.3 3.3 3.3 3.3 - 3.3 3.3 3.3 - 3.3 3.3 3.3 3.3 3.3 3.3 - 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 O - I O - O O O - O O O - O O O - O O O - - -
I/O
81 MHz clock return path input 81 MHz memory clock output supply for pad ring memory address memory address memory address ground for pad ring memory address memory address memory address supply for pad ring memory address memory address memory address ground for pad ring memory address memory address memory address ground for core logic supply for core logic supply for pad ring IC test interface IC test interface horizontal synchronization input and output vertical synchronization input and output ground for pad ring YUV video output at 27 MHz YUV video output at 27 MHz YUV video output at 27 MHz YUV video output at 27 MHz supply for pad ring YUV video output at 27 MHz YUV video output at 27 MHz YUV video output at 27 MHz YUV video output at 27 MHz IC test interface indicator for graphics information output IC test interface
SDRAM_ADDR11 88
SDRAM_ADDR10 91
I/O I/O I/O I/O - O/Z O/Z O/Z O/Z - O/Z O/Z O/Z O/Z I/O O I/O
1997 Jan 29
8
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
SAA7201
SYMBOL VDDA VSSA VSS13 CLK VSS14 TCLK TRST TMS TDO TDI VDD13 TEST4 TEST3 TEST2 TEST1 TEST0 VDD14 RESET FSCLK VDDCO4 VSSCO4 SCLK SD VSS15 WS SPDIF ERROR V_STROBE VDD15 AV_DATA0 AV_DATA1 AV_DATA2 AV_DATA3 VSS16 AV_DATA4 AV_DATA5 AV_DATA6 AV_DATA7 A_STROBE VDD16
PIN 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 supply for analogue blocks ground for analogue blocks ground for pad ring 27 MHz clock input ground for pad ring
DESCRIPTION - -
V 3.3 - - - I - I I I O I -
I/O
3.3 - 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 - 3.3 3.3 - 3.3 3.3 5.0 5.0 3.3 5.0 5.0 5.0 5.0 - 5.0 5.0 5.0 5.0 5.0 3.3
boundary scan test clock input boundary scan test reset input boundary scan test mode select input boundary scan test data output boundary scan test data input supply for pad ring IC test interface IC test interface IC test interface IC test interface IC test interface supply for pad ring hard reset input (active LOW) 256 or 384 fs (audio sampling) output supply for core logic ground for core logic serial audio clock output serial audio data output ground for pad ring word select output digital audio output flag for bitstream error input video strobe input supply for pad ring MPEG input port for PES data MPEG input port for PES data MPEG input port for PES data MPEG input port for PES data ground for pad ring MPEG input port for PES data MPEG input port for PES data MPEG input port for PES data MPEG input port for PES data audio strobe input supply for pad ring
I/O I/O I/O I/O I/O - I O/Z - - O/Z O/Z - O/Z O/Z I I - I I I I - I I I I I -
1997 Jan 29
9
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
SAA7201
159 A_STROBE
158 AV_DATA7
157 AV_DATA6
156 AV_DATA5
155 AV_DATA4 154 VSS16
153 AV_DATA3
152 AV_DATA2
148 V_STROBE 147 ERROR
151 AV_DATA1
150 AV_DATA0 149 VDD15
142 SCLK 141 VSSCO4 140 VDDCO4
138 RESET 137 VDD14
160 VDD16
139 FSCLK
132 TEST4 131 VDD13
126 TCLK 125 VSS14
127 TRST
130 TDI 129 TDO
128 TMS
MUX CPU_TYPE DMA_ACK DMA_REQ DMA_DONE DMA_RDY VSS1 CS DS AS R/W DTACK VDD1 IRQ0 IRQ1 IRQ2 IRQ3 VSS2 VSSCO1 VDDCO1 DATA0 DATA1 DATA2 DATA3 VDD2 DATA4 DATA5 DATA6 DATA7 VSS3 DATA8 DATA9 DATA10 DATA11 VDD3 DATA12 DATA13 DATA14 DATA15 VSS4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
124 CLK
handbook, full pagewidth
123 VSS13 122 VSSA 121 VDDA 120 TEST5 119 GRPH 118 TEST6 117 YUV7 116 YUV6 115 YUV5 114 YUV4 113 VDD12 112 YUV3 111 YUV2 110 YUV1 109 YUV0 108 VSS12 107 VS 106 HS 105 TEST7 104 TEST8 103 VDD11 102 VDDCO3 101 VSSCO3 100 SDRAM_ADDR3 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 SDRAM_ADDR2 SDRAM_ADDR4 VSS11 SDRAM_ADDR1 SDRAM_ADDR5 SDRAM_ADDR0 VDD10 SDRAM_ADDR6 SDRAM_ADDR10 SDRAM_ADDR7 VSS10 SDRAM_ADDR11 SDRAM_ADDR9 SDRAM_ADDR8 VDD9 CP81M CP81MEXT VSS9 READO
MGD321
136 TEST0
135 TEST1 SDRAM_DATA5
134 TEST2
SAA7201
SDRAM_DATA12
SDRAM_DATA11
SDRAM_DATA10 VSS7
SDRAM_DATA3
SDRAM_DATA4 VDD6
133 TEST3
145 WS 144 VSS15
146 SPDIF
143 SD
SDRAM_DATA6 SDRAM_DATA9
SDRAM_DATA7 VDD7
SDRAM_DATA8
SDRAM_UDQ VDD8
SDRAM_WE SDRAM_CAS VSS8
ADDRESS1
ADDRESS2
ADDRESS3
ADDRESS4 VDD4
ADDRESS5 ADDRESS6
ADDRESS7
ADDRESS8 VSS5
SDRAM_RAS
Fig.2 Pin configuration.
1997 Jan 29
SDRAM_DATA13 VSS6
SDRAM_DATA15
SDRAM_DATA14
SDRAM_DATA0
SDRAM_DATA1 VDD5
SDRAM_DATA2
VSSCO2 VDDCO2
10
READI
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
FUNCTIONAL DESCRIPTION General The SAA7201 is an MPEG2 decoder which combines audio decoding, video decoding and enhanced region based graphics. The decoder operates with a single 16 Mbit external synchronous dynamic random access memory (SDRAM) and runs from a single external 27 MHz clock. Due to the optimized memory control for MPEG2 decoding, more than 1 Mbit is available for graphics in 50 Hz systems. MPEG2 data can be accepted up to 9 Mbytes/s through a dedicated byte wide interface. The data on this interface can be either in PES (Packetized Elementary Stream), MPEG1 packet or ES (Elementary Stream) format as described in Chapter "References". Two additional strobe signals distinguish between audio and video data. The internal video decoder is capable of decoding all MPEG compliant streams up to main level main profile as specified in Chapter "References". The audio decoder implements 2 channel audio decoding according to the standards in Chapter "References". All real time audio/video decoding and synchronization tasks are performed autonomously, so the external microcontroller only needs to perform high-level tasks like initialization, status monitoring and trick mode control. The main support task of the external microcontroller concerns the control of the graphical unit. This unit should
SAA7201
be supplied with bit-maps, determining the contents of the graphical regions and by a simple set of instructions determining the appearance of the graphical data on the screen. Most graphical information should be stored in the external memory which implies multiple data transfers between CPU and the external memory. By performing these data transfers on a direct memory access (DMA) basis, full bit-maps can be transferred within one video frame period. The video output, containing a mix of MPEG video and graphical data, is at a YUV multiplexed format which can be directly connected to an external composite video encoder. The audio output, containing a mix of MPEG audio and programmable `beeps', is in a serial, I2S or Japanese format which can be directly supplied to most commercially available up-sampling audio DA converters. A functional block diagram of the decoder is given in Fig.1. Its application environment is depicted in Fig.24. In the following sections, a brief description of the individual internal blocks of the MPEG2 decoder will be given. Audio/video interface In a basic set-top box application the SAA7201 receives audio and video PES data in a byte wide format at rates up to 9 Mbytes/s. A timing diagram is shown in Fig.3. Next to the 8-bit wide data bus an audio and video strobe is expected at the input. Erroneous data may be flagged via the error indicator.
handbook, full pagewidth AV_DATA
(0 to 7) 25 ns V_STROBE
video byte (n) 25 ns
video byte (n + 1)
audio byte (m)
111 ns A_STROBE
ERROR
MGD323
Fig.3 Timing diagram of parallel input mode.
1997 Jan 29
11
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
SAA7201
handbook, full pagewidth
AV_DATA0
video bit (n + 6) 25 ns 25 ns
video bit (n + 7)
audio bit (m + 0) first bit of a byte
V_STROBE 50 ns A_STROBE
MGD324
Fig.4 Timing diagram of serial input mode.
Alternatively data can be received in a 1-bit serial format at rates up to 20 Mbit/s. In this mode, data is input at the LSB input of the AV_DATA bus. Audio and video data must be input in multiples of 8 bits. The first bit after switching from audio to video (or the other way around) must be the first bit of a byte since this transition will be used for the internal bit-to-byte conversion. Audio/video data can also be received via the CPU interface in 8 or 16-bit mode. The peak rate is 27 Mbytes/s in bursts of 128 bytes with a sustained rate up to 9 Mbytes/s. However, the MPEG bit rate is still limited to 15 Mbit/s for video and 448 kbit/s for audio. Independent of the input mode all audio and video input data are stored sequentially in the audio or video input buffer area of the external memory. The audio and video data can be either in MPEG2 PES, MPEG1 packet or ES format. Memory interface unit The memory interface takes care of addressing and control of the 16-Mbit external SDRAM. The SDRAM should be either JEDEC compliant either the `lite/PC' version. Due to memory communication requirements this interface runs at 81 MHz. The SDRAM types used with the SAA7201 should be organized as 1M x 16, split internally in two banks, each having 2048 pages of 256 words of 16 bits. The target SDRAM type is NEC PD 4516161G5-A12-7FJ (83 MHz JEDEC version) or NEC PD 4516421G5-A83-7FJ-PC (83 Mhz PC version).
Clock generation The clock generation unit generates all the internal processing clocks, the clock for the system time base counter and the audio oversampling clock for the audio DAC. For this purpose a non-integer divider plus a PLL is implemented. In order to get reliable audio and video decoding the 27 MHz input clock should be locked externally to the MPEG time base. Host interface system The host interface system handles the communication between on one side the SAA7201 plus SDRAM and on the other side the external CPU. The interface consists of a 16-bit wide data bus plus 8 address lines. It is compatible with both Motorola's 68xxx and Intel's x86 family. An optimized interface with the SAA7208 is also supported. Via this interface a fast direct access to a large number of internal status and data registers can be achieved. Moreover, the external SDRAM can be accessed via a specific register in combination with an internally implemented auto increment counter. The access to the external SDRAM is guaranteed up to a sustained data rate of 9 Mbyte per second. However, in practice the achievable data rate can be much higher. Next to the data and address lines, 4 interrupt lines are part of the host interface bus. Each interrupt line can monitor up to 32 internal events which all can be masked individually. Examples of internal events are audio/video bit stream information, decoder status, internal error conditions and input buffer occupation. The latter may be very useful in interactive applications to serve as input data request line.
1997 Jan 29
12
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
System time base unit The system time base unit serves as a timing master for all internal processes. It consists of two 24-bit wide System Time Clock (STC) counters, running at 90 kHz. The STCs will be used as internal synchronization reference for audio and video.The contents of the STC can be loaded by the external CPU which should insure that the phase of the SAA7201 internal STC is identical to the main system time clock in the system demultiplexer. The CPU should correct for possible latency problems. Because two counters are implemented, the previous time base reference which might still be required as reference for some time in case of time base discontinuity, can be maintained. Thus all information for audio/video synchronization is available in the decoder chip and only minor support of the external controller is required. The synchronization of graphics for e.g. subtitling, should be controlled by the external CPU. Video input buffer and synchronization control The size and position of the video input buffer in the external SDRAM is programmable. By default 2.6 Mbit/s are reserved for the video input buffer but in principle any other value can be programmed. The current fullness of the video input buffer can be monitored by the CPU and an internal interrupt will be generated is case of either near over- or near underflow.
SAA7201
Data retrieval from the input buffer can be controlled by DTS time stamps parsed from the PES or MPEG1 packet stream. For those frames where no DTS time stamp is present in the video bitstream a DTS is emulated by the SAA7201. Obviously this emulation mode can also be used when the input stream is a video elementary stream (ES). The latter case should be handled by start and stop decode commands from the CPU. The external CPU can select to retrieve the video PES header and/or video PES private data for further software processing. Audio input buffer and synchronization control The audio input buffer and synchronization control basically behaves identical to its video counter part. The default buffer size is 64 kbit in this case. Synchronization will be controlled by PTS time stamps in the audio Packetized Elementary Stream. Also in this case an PTS emulation or a free running start/stop controlled mode are supported. Audio decoder A functional block diagram for the audio decoding part is depicted in Fig.5.
handbook, full pagewidth
BUFFER AND SYNC UNIT DRAM-bus 81 MHz AUDIO CLOCK GENERATOR
MPEG AUDIO DECODER
+
OUTPUT INTERFACE
Sony or I2S-bus SPDIF
AUDIO BEEP
Audio decoding unit
MGD325
Fig.5 Audio decoding unit.
1997 Jan 29
13
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
Audio decoding will be performed at a clock locked to the video decoding clock and only the output interface is running on the audio oversampling clock. The audio decoder unit performs the decoding of the selected MPEG audio stream in a range from 8 up to 448 kbit/s in a fixed or variable bit rate format. Decoding is restricted to 2 channel, layer I, II MPEG audio at sampling frequency of 48.0, 44.1, 32.0, 24.0, 22.05 or 16.0 kHz. The audio decoder support the stop, mute, and skip function to support insertion Apart from basic MPEG processing the audio decoder core contain also: * Support for: stop, mute and skip function. * Fully parameterized dynamic range compression unit to decrease the dynamic range of the output signal on audio frame basis. Depending on the power level a programmable amplification and offset may be applied. * Fully programmable base band audio processing unit to control the gain in both output channels independently and/or to mix both channels. * MPEG de-emphasis filtering on the output data, thus avoiding the need of external analog de-emphasis filter circuitry. * Storage buffer for the last 54 bytes of each audio frame. The CPU can retrieve eventual ancillary data from this buffer.
SAA7201
The output of the audio decoder unit can be mixed with square waveform audio signals which are generated by a beep generator. Programmable parameters for the beep generator are amplitude, frequency and duration. The audio output interface module produces stereo base band output samples on two different outputs at the same time: * Serial digital audio in I2S-bus or in Japanese format in 16, 18, 20 or 22-bit * SPDIF (Sony/Philips Digital Interface). Any of the two outputs may be enabled or set to high impedance mode. The I2S-bus format with 18-bit sample precision is shown in Fig.6. The difference between I2S-bus and the Japanese format is that I2S-bus is MSB aligned whereas the Japanese format is LSB aligned. The 1-bit serial interface SPDIF contains 64-bit per audio sample period. Complete frames must be transmitted at the audio sample rate. Not only left/right information but also validity flags, channel status, user data and parity information is contained in an SPDIF frame (see Chapter "References").
handbook, full pagewidth
SCLK
WS
0
31
32
63
SD
b17
b0 left sample n
b17
b0
b17
b0
MGD326
right sample n
left sample n + 1
MSB aligned
Fig.6 I2S-bus format with 18-bit sample precision.
1997 Jan 29
14
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
Video decoder The video decoding unit provides all actions required for compliant decoding of MPEG2 main level, main profile coded video bit streams. The decoding process consists of fixed and variable length decoding, run length decoding, inverse quantization, inverse discrete cosine transformation, motion compensation and interpolation. In general the arithmetic decoding result is stored as reference picture in the external memory. Decoded B-frames are only stored for the conversion from the frame coded macro block (MB) to the scanning line format. In many cases a field storage is sufficient for this conversion but in some cases the user might decide to use a full frame storage to enable chroma frame up-conversion or full performance 3 : 2 pull-down in 60 Hz systems. Obviously when using less memory for the video decoding process more memory is available for non-video decoding tasks.
SAA7201
The Frame Buffer Management unit (FBM) manages the allocation of frame buffers in external SDRAM for both video decoding and display unit and can be programmed to use less memory in not fully MP@ML bitstreams: smaller pictures (e.g. 544 x 576), simple profile, etc. Apart from decoding compliant MPEG video streams the decoder deals with some trick modes. Supported are field or frame freeze at I or P pictures or freeze field on B-pictures. In the latter case decoding will continue as a background process and the output can be restarted at any moment. When receiving non-compliant MPEG streams the decoder can be switched to a scanning mode in which only I or I + P frames are decoded while skipping all other pictures. In the single step mode, the decoder decodes just one frame and awaits a next step command. The functional diagram of the video decoding unit is shown in Fig.7.
handbook, full pagewidth
from input buffer
VLD
IZZ
IQ
IDCT INTERP to external memory
FLD MC from reference memory FBM to display unit
MGD327
Fig.7 Video decoding unit.
1997 Jan 29
15
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
Graphics unit The SAA7201 incorporates the display support for pixel based graphics. Possible applications are the user interface, logos and subtitling. Graphical data should be grouped logically in regions and will be displayed in boxes at the screen. The definition of each region in the decoder consists of four parts being a region descriptor, a top-field descriptor, a bottom-field descriptor and a table-data descriptor: * The region descriptor contains information relevant for the full region like format, size, position and pointers to the other descriptors.
SAA7201
* The top-field and bottom-field descriptor contain a pixel based bit-map for the contents of that region for both fields independently. The bit-maps can be stored in either straight forward or in a compressed bit-map format. * The table-data descriptor defines the tables to be used for the transformation of bit-maps to display colours. All descriptors should be loaded under control of the external CPU in the external memory. The appearance of graphical data at the display is determined by the assembly of region descriptors in a so called display list. An example of such a display list for the 4 regions example is shown in Fig.9.
handbook, full pagewidth
H-start (2)
H-size (2)
REGION-1 (VBI-SIGNALS) V-start (2)
V-size (2)
REGION-2 active video REGION-3 (256 ENTRY CLUT) REGION-4
active video
MGD328
Fig.8 Graphics unit.
handbook, full pagewidth
gfx anchor address
128 bit DESCRIPTOR 1 DESCRIPTOR 2 DESCRIPTOR 3 DESCRIPTOR 4 eodl
position, size, format pointers to locations in SDRAM
PIXEL DATA PIXEL DATA top-field MAP
MGD329
bottom-field
CLUT table data
Fig.9 Display list.
1997 Jan 29
16
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
Basically there is no restriction on the number of different regions but because regions may not vertically overlap the practical limit will be the number of lines within a field. However, one should realize that each region requires its own 128-bit region descriptor. The display list will be scanned twice per frame, once for each display field. The region descriptors should be ordered properly in the external SDRAM, starting from the graphics anchor address. The last descriptor in the list must have the end of display list indicator set. Multiple pixel bit-maps, CLUTs and map tables may be stored in the external memory but per region only two bit-maps (one for each fields) and two tables (CLUT + map table) may be used. Obviously bit-maps and tables may be shared by multiple regions. Pixel data bit-maps can be described in 2, 4 or 8 bit/pixel in either a direct bit-map or coded in a one-dimensional (H) variable and run length encoded format according the pixel-data-sub-block syntax as specified in Chapter "References" and illustrated in Chapter "Appendix". The actual coding format is specified in the region descriptor for each region thus allowing different coding schemes within a picture. During display the 2, 4 and 8 bit/pixel bit-maps will be transformed, eventually with run length decoding, via a table look-up mechanism into a 4, 16 or 256 different YUV colours with 8-bit resolution for each component plus a factor T for mixing of graphics and MPEG video. In order to obtain maximum flexibility two cascaded tables are active in this bit-map to pixel conversion as indicated in Fig.10.
SAA7201
The tables are retrieved from the external memory just before the region is going to be displayed. One table per region can be updated and for small tables this occurs during the horizontal blanking interval. However, updating a 256 entry CLUT may take about one line period which means that a spatial separation of one line with the previous region is mandatory in this case. If the required tables for a certain region are already stored in the local memory, the table down load action can be skipped. Additionally some special bits can be set in the region descriptor. * Transparency shift: this parameter overrules the pixel based transparency in order to support fading of the entire graphical region. * Zoom: this parameter initiates horizontal pixel repetition. It should be noted that a copy of pixels in vertical direction can be achieved by pointing to a single bit-map for both fields. Regions can also be defined in the vertical blanking interval. In combination with 8 bit/pixel coding, arbitrary test signals on 13.5 MHz grid can be programmed. Possible application areas are teletext, closed caption, wide screen signalling bits, Video Programming Signals (VPS) and Vertical Interval Test Signals (VITS). As indicated above multiple regions can be specified in a display list which will be scanned sequentially every frame. In case of stationary graphics no updates of the display list are required, but the external CPU can update it dynamically to achieve scrolling and/or fading of one or more graphical boxes. The display list mechanism also allows for non real time transfer of large bit-maps by keeping that region out of the display list during loading.
8 LSBs
handbook, full pagewidth
4 LSBs 8 4 LSBs MAP TABLE 4 to 8 8 8 2 LSBs 2 LSBs MAP TABLE 2 to 8 8 CLUT 8 8 8 8 Y U V T
MGD330
Fig.10 Bit-map to pixel conversion.
1997 Jan 29
17
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
CURSOR PROCESSING Additionally to the above defined graphics boxes one cursor can be activated on the screen. Since the cursor data is fully stored locally, no overlapping restriction apply to this box so the cursor can moved over the entire screen. The cursor can be as large as 1 kpixel with a 2 bits/pixel colour depth. Obviously data transfer can be done on DMA basis and need only be performed when a cursor is required or when its contents must be modified. The cursor XY dimensions (where the Y dimension refers to frame lines) can be selected between 8 x 128, 16 x 64, 32 x 32, 64 x 16 and 128 x 8. On top of these shapes, a zoom with a factor 2 can be applied in both directions independently. The cursor pixels will be translated via a 4-entry CLUT to YUV colours and a transparency factor T. The resolution of the YUV parameters is 6, 4, 4 bits respectively. The T parameter is coded in 2 bits to enable the mixing with video and graphics in 4 steps being 100% (cursor only), 50%, 25% and 0% (fully transparent cursor). Display unit Before feeding the MPEG decoded and graphical data to the output, a display unit re-formats the MPEG specific 4 : 2 : 0 format to CCIR-601 4 : 2 : 2 format and performs a mixing between video and graphics where required. The output picture can be up to 720 x 576 pixels at 50 Hz or 720 x 480 pixels at 60 Hz. A schematic representation of this unit is shown in Fig.11. * In a first step a selected window can be retrieved from the decoded MPEG data. This might be useful for e.g. pan and scan operations for aspect ratio conversion.
SAA7201
* In case the resulting number of pixels per line does not match the 720 pixels/line output format a horizontal scaler can be activated. This scaling unit can transform any number of bits below 720 to the required output format. Internally a poly-phase filter is used which performs a 64 phases interpolation. Not only up-conversion but also down-conversion is supported up to a scaling by a factor 2. Thus horizontal scaling can be performed in a range from 0.5 up to 64. In practice the maximum up-conversion factor will be less or equal to 4. * In vertical direction the picture can be expanded or scaled down, in both cases by a factor 2. Expansion with a factor 2 might be relevant for the up-conversion of SIF resolution pictures to full screen. The factor 2 scaling, if combined with the appropriate horizontal scaling, results is 14 picture thus freeing-up a large screen area for graphics. This might be very useful for electronic program guide applications. It should be noted that in case of picture compression an anti-aliasing filter can be activated. * Shifting: when the resulting MPEG picture is smaller than the 720 x 576 (480) display format, this picture can be located anywhere on the display screen. Moreover, the non-covered area can be given any background colour. * Clipping: the amplitude of the MPEG decoded and re-scaled video signal is kept within the range 16 to 235 for luminance and 16 to 240 for both chrominance components.
handbook, full pagewidth
MPEG decoded picture
WINDOW EXTRACTION
SCALING
SHIFTING
CLIPPING
CHROMA UP-CONVERSION
64 STEP MIXER
4 STEP MIXER
OUTPUT FORMAT
to digital CVBS encoder
GRAPHICS
CURSOR
MGD331
Fig.11 Display unit.
1997 Jan 29
18
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
* The chroma up-conversion unit converts the MPEG 4 : 2 : 0 format into the at the output required 4 : 2 : 2 format. This vertical up-conversion is performed by a simple 8-phase interpolation between two adjacent lines. * The mixer units combine MPEG video with graphics and cursor information in two steps. In a first step the MPEG decoded information is mixed with graphical information. Mixing can be done at pixel basis in 64 steps and is controlled by the internally implemented colour look up table. In a second step, the video plus graphics can be mixed in 4 steps with the internally generated cursor. * The output formatting unit performs two main tasks, i.e. synchronization and formatting. Synchronization is characterized by three signals being horizontal (H), vertical (V) and field parity (FP), all having programmable length and polarity.
SAA7201
Since the decoder can operate in master or slave mode, the synchronization signals can be generated by the decoder or should be delivered by an external device. In both cases the length and polarity should be programmed internally. The video output samples are supplied in a multiplexed YUV format to the output. Next to this byte wide YUV stream, which can directly be supplied to most commercially available composite video encoder ICs, three additional signals are delivered at the output. HREF indicates all active samples; CREF can flag any combination of pixels: U, V, Yodd and/or Yeven; GRPH flags all the pixels inside a graphical box. Additionally the full YUV bus can be set to a HIGH impedance state under control of the signal YUV_ENA. This might be useful for multiplexing the MPEG decoder output with any other signal source on static basis.
handbook, full pagewidth
CLK
YUV
'128'
'16'
U0
Y0
V0
Y2
HREF
CREF (example)
GRPH
MGD332
Fig.12 Timing diagram of graphics information output.
1997 Jan 29
19
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
JTAG The SAA7201 supports the standard Boundary Scan test instructions: bypass, extest, sample, intest, runbist, idcode. Memory requirements As indicated before the MPEG source decoder operates with 16 Mbit of external memory. Several processes require access to the external memory, mostly being the video decoding process. In normal main level, main profile video applications about 1.2 Mbit of memory space is free for non-video processes. In practice most of this capacity will be used for graphics. In combination with the internal variable length decoding, full screen graphics at 8-bit per pixel is feasible. Moreover, by having introduced a flexible memory allocation procedure the available memory capacity for graphics may be enlarged when decoding lower resolution MPEG pictures or when the input bit rate is less than 15 Mbit/s. Table 1
SAA7201
Obviously for graphics-only applications all 16 Mbit can be used for the storage of bit-maps and look-up tables. In Table 1 an overview is given of the required memory capacity for some user defined modes. In 50 Hz systems memory capacity can be saved by restricting the chroma vertical interpolation to field interpolation. This mode would only bring some extra chroma resolution in case the input stream contains progressive coded pictures. In 60 Hz systems the reduction of storage capacity for B-frames to field capacity has not only consequences for the chroma vertical interpolation but also for the 3 : 2 pull-down operation mode. The operation repeat-first-field is not possible in all cases and a modified 3 : 2 pull-down is performed under the control of the SAA7201. The user may decide to use this modified 3 : 2 pull-down mode in order to have more memory available for OSD or graphics.
Required memory capacity for some user defined modes System Bit rate (R) Chroma interpolation 3 : 2 pull-down Picture format frame n.a. 720 x 576 64 kbit 1835 kbit 600 kbit 300 kbit 13456 kbit 16255 kbit 522 kbit 50 Hz 15 Mbit/s field n.a. 720 x 576 64 kbit 1835 kbit 600 kbit 300 kbit 12719 kbit 15518 kbit 1259 kbit field n.a. 544 x 576 64 kbit 1835 kbit 400 kbit 200 kbit 9609 kbit 12108 kbit 4669 kbit 60 Hz 15 Mbit/s frame full MPEG 720 x 480 64 kbit 1835 kbit 500 kbit 250 kbit 12441 kbit 15090 kbit 1687 kbit field modified 720 x 480 64 kbit 1835 kbit 500 kbit 250 kbit 10634 kbit 13292 kbit 3485 kbit 9 Mbit/s field modified 720 x 480 64 kbit 1835 kbit 300 kbit 150 kbit 8042 kbit 10391 kbit 6386 kbit
Audio input buffer Video input buffer Video implementation buffer (R/P) Slave synchronization buffer (R/2P) Reference and decoded picture Total for video + audio Remains for OSDG (224 = 16777 kbit)
1997 Jan 29
20
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC134). SYMBOL VDD Vmax Ptot Tstg Tamb PARAMETER supply voltage (on all supply pins) maximum voltage on all pins total power dissipation storage temperature operating ambient temperature Tamb = 25 C CONDITIONS 3.0 0 - -55 0 MIN. MAX. 3.6 5.5 tbf +150 +70
SAA7201
UNIT V V W C C
THERMAL CHARACTERISTICS SYMBOL Rth j-a PARAMETER thermal resistance from junction to ambient in free air VALUE 30 UNIT K/W
1997 Jan 29
21
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
CHARACTERISTICS SYMBOL Supply VDD IDD Inputs VIH VIL ILI Ci Outputs VOH VOL CLK timing TC tr tf tsu th tsu(A-CS) th(A-CS) tsu(D-W) tsu(D-R) trel(D) th(CT) tW(ACK) trel(ACK) td(ACK-R) td(ACK-W) tW(RW) th td CL cycle time duty factor rise time fall time 37.036 40 2 2 37.037 - - - - - - - - - - - - - - - - - - - HIGH level output voltage LOW level output voltage 2.4 - - - - 0.4 HIGH level input voltage LOW level input voltage leakage current input capacitance 2.0 -0.5 - 0 - - - - supply voltage supply current 3.0 - 3.3 tbf 3.6 - PARAMETER MIN. TYP.
SAA7201
MAX.
UNIT
V mA
VDD + 2.0 0.8 20 10
V V mA pF
V V
37.038 60 4 4 - - - - - - 10 - - 10 125 75 -
ns % ns ns
Input timing with respect to CLK rising edge set-up time hold time 8 0 ns ns
Timing (see Figs. 13, 14, 15, 16, 17, 18, 19, 20, 21, 21 and 21) address/CS set-up time address/CS hold time data write set-up time data read set-up time data release time control signal hold time acknowledge pulse width acknowledge release time delay time for acknowledge read delay time for acknowledge write write/read pulse width 20 75 20 20 0 0 25 0 96 48 25 ns ns ns ns ns ns ns ns ns ns ns
Output timing with respect to CLK rising edge hold time delay time load capacitance 3 th 10 td 20 30 ns ns pF
1997 Jan 29
22
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
SAA7201
handbook, full pagewidth
ADDRESS (8 to 1)
ADDRESS
tsu(A-CS) CS
th(A-CS)
R/W tW(RW) DS td(ACK-W) DTACK tsu(D-W) DATA (15 to 0) DATA
MGD333
trel
trel(ACK)
th(D)
tW(ACK)
Fig.13 Motorola write timing (non-multiplexed).
handbook, full pagewidth
ADDRESS (8 to 1)
ADDRESS
tsu(A-CS) CS
th(A-CS)
R/W tW(RW) DS td(ACK-R) tW(ACK) trel
trel(ACK)
DTACK tAR DATA (15 to 0) tsu(D-R) DATA
MGD334
trel(D)
Fig.14 Motorola read timing (non-multiplexed).
1997 Jan 29
23
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
SAA7201
handbook, full pagewidth
ADDRESS (8 to 1)
ADDRESS
tsu(A-CS) CS
th(A-CS)
tW(RW) R/W td(ACK-W) RDY trel(ACK) tsu(D-W) DATA (15 to 0) DATA th(D)
trel
MGD335
Fig.15 Intel write timing (non-multiplexed).
handbook, full pagewidth
ADDRESS (8 to 1)
ADDRESS
tsu(A-CS) CS
th(A-CS)
tW(RW) R/W td(ACK-R)
trel
tsu(D-R)
RDY trel(ACK) tAR DATA (15 to 0) DATA
MGD336
trel(D)
Fig.16 Intel read timing (non-multiplexed).
1997 Jan 29
24
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
SAA7201
handbook, full pagewidth
CS
tsu(A-CS) DMA_REQ
th(A-CS)
tW(RW) DMA_ACK td(ACK-W) DMA_RDY tsu(D-W) DATA (15 to 0) DATA th(D)
trel
trel(ACK)
MGD337
Fig.17 DMA read access.
handbook, full pagewidth
CS
tsu(A-CS) DMA_REQ
th(A-CS)
tW(RW) DMA_ACK td(ACK-R) DMA_RDY tAR DATA (15 to 0) tsu(D-R) DATA
trel
trel(ACK)
trel(D)
MGD338
Fig.18 DMA write access.
1997 Jan 29
25
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
SAA7201
handbook, full pagewidth
DMA_REQ
DMA_ACK
tsu(A-CS) DMA_DONE
th(A-CS)
MGD339
Fig.19 DMA_DONE timing.
handbook, full pagewidth
DATA (15 to 0) tsu(SDR-D)
DATA trel(D)
RDY tW(ALE) ALE tsu(A-CS) ADDRESS (8 to 0) th(CS-ALE) CS th(A-CS) ADDRESS th(CS) tsu(ALE-SDR) tW(SDR)
SYSRD
MGD919
Fig.20 SAA7208 mode; read timing.
1997 Jan 29
26
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
SAA7201
handbook, full pagewidth
DATA (15 to 0)
DATA tW(D-SDR) th(D-SDR)
RDY tW(ALE) ALE tsu(A-CS) ADDRESS (8 to 0) th(CS-ALE) CS ADDRESS th(CS) th(A-CS) tW(SDR)
SYSRD
MGD918
Fig.21 SAA7208 mode; write timing.
1997 Jan 29
27
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
SAA7201
handbook, full pagewidth
DATA (15 to 0)
DATA tsu(D-SDR) th(D-SDR) tsu(D-SDR)
DATA th(D-SDR)
RDY tW(ALE) ALE tsu(A-SDR) ADDRESS (8 to 0) th(CS-ALE) ADDRESS th(A-SDR) tsu(A-SDR) th(A-SDR) ADDRESS th(CS) tW(SDR) tW(SDR)
trel(SDR)
CS
SYSRD
MGD920
Fig.22 SAA7208 mode; burst write timing.
1997 Jan 29
28
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
SAA7201
handbook, full pagewidth
AD(read)
ADDRESS
DATA
tAR AD(write) tsu(A-S) CS ADDRESS th(A-CS) DATA
tsu(D-R)
tsu(D-W)
th(D)
tW(ACK) RDY tW(A-CS) ALE trel(D) trel(ACK)
RD tW(RW) trel
WR
MGD341
Fig.23 Intel read/write timing multiplexed.
REFERENCES 1. MPEG ISO/IEC 11172-1 International standard; MPEG-1 systems. 2. MPEG ISO/IEC 13818-1 International standard; MPEG-2 systems. 3. MPEG ISO/IEC 11172-2 International standard; MPEG-1 Video. 4. MPEG ISO/IEC 13818-2 International standard; MPEG-2 Video. 5. MPEG ISO/IEC 11172-3 International standard; MPEG-1 Audio. 6. MPEG ISO/IEC 13818-3 International standard; MPEG-2 Audio. 7. DVB subtitling system; working draft 2.0; TM 1398 rev 2.
1997 Jan 29
29
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
APPLICATION INFORMATION
SAA7201
handbook, full pagewidth
4 Mbit EPROM
4 Mbit DRAM
16 Mbit SDRAM address data 16 8+3 12 16 control
INT SAA7208 (DEMUX/MIPS) 27.0 MHz 8 SAA7201 strobe H,V valid 27 MHz H, V, FP TTX/TTXRQ high speed data SAA7183 (EURO-DENC) I2C-bus YUV I2C-bus AUDIO DA L R
CVBS Y/C RGB
MGD342
Fig.24 Application diagram.
1997 Jan 29
30
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
APPENDIX Syntax of pixel-data-sub-block data type 2 bit/pixel 0001 0000 01 10 11 00 01 00 00 01 00 1L LL CC 00 00 10 LL LL CC 00 00 11 LL LL LL LL CC 4 bit/pixel 0001 0001 0001 1111 0000 1100 0000 1101 0000 0LLL (L>0) 0000 10LL CCCC 0000 1110 LLLL CCCC 0000 1111 LLLL LL11 CCCC 8 bit/pixel 0001 0010 00000001 11111111 00000000 0LLLLLLL 00000000 1LLLLLLL CCCCCCCC pixel-code-string of N-coded words 1 pixel in colour 1 1 pixel in colour 2 1 pixel in colour 3 1 pixel in colour 0 2 pixels in colour 0 L pixels (3 to 10) in colour C L pixels (12 to 27) in colour C L pixels (29 to 284) in colour C 1 pixel in colour 1 1 pixel in colour 15 1 pixel in colour 0 2 pixels in colour 0 L pixels (3 to 9) in colour 0 L pixels (4 to 7) in colour C L pixels (9 to 24) in colour C L pixels (25 to 280) in colour C 1 pixel in colour 1 1 pixel in colour 255 L pixels (1 to 127) in colour 0 L pixels (3 to 127) in colour C 00 00 00
SAA7201
end of string
0000 0000
00000000-- --00000000
1997 Jan 29
31
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
PACKAGE OUTLINE QFP160: plastic quad flat package; 160 leads (lead length 1.95 mm); body 28 x 28 x 3.4 mm; high stand-off height
SAA7201
SOT322-1
c
y X
A 120 121 81 80 ZE
e E HE A A2 A1
Q (A 3) Lp L detail X
wM bp pin 1 index 160 1 bp D HD wM ZD B vM B 40 vM A 41
e
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 3.95 A1 0.40 0.25 A2 3.70 3.15 A3 0.25 bp 0.40 0.25 c 0.23 0.13 D (1) 28.1 27.9 E (1) 28.1 27.9 e 0.65 HD 32.2 31.6 HE 32.2 31.6 L 1.95 Lp 1.1 0.7 Q 1.70 1.55 v 0.3 w 0.15 y 0.1 Z D(1) Z E (1) 1.5 1.1 1.5 1.1 8 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT322-1 REFERENCES IEC JEDEC MO112DD1 EIAJ EUROPEAN PROJECTION
ISSUE DATE 93-08-25 95-02-04
1997 Jan 29
32
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Reflow soldering Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Handbook" (order code 9397 750 00192). Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. Wave soldering
SAA7201
Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering the following packages: QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1997 Jan 29
33
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA7201
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
1997 Jan 29
34
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
NOTES
SAA7201
1997 Jan 29
35
Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 1949 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615800, Fax. +358 9 61580/xxx France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 23 53 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS, Tel. +30 1 4894 339/239, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd. Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722 Indonesia: see Singapore Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Rua do Rocio 220, 5th floor, Suite 51, 04552-903 Sao Paulo, SAO PAULO - SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 829 1849 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 3 301 6312, Fax. +34 3 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 632 2000, Fax. +46 8 632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2686, Fax. +41 1 481 7730 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2870, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1997
Internet: http://www.semiconductors.philips.com
SCA53
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
547047/1200/01/pp36
Date of release: 1997 Jan 29
Document order number:
9397 750 00989

▲Up To Search▲

Price & Availability of SAA7201H

	To Download SAA7201H Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .